1. Field of the Invention
The present invention relates to the forming of a thin single-crystal semiconductor layer portion separated from a single-crystal semiconductor substrate by a vacuum or by one or several non single-crystal layers.
2. Discussion of the Related Art
In many semiconductor devices, it is desirable to have at least one thin single-crystal semiconductor layer separated from a single-crystal semiconductor substrate by a vacuum or one or several layers of different natures and especially insulating and/or conductive layers.
For this purpose, a known method comprises the growth of a first sacrificial single-crystal layer on a single-crystal substrate and of a second single-crystal layer on the first one. After this, the sacrificial layer is removed and the volume that it took up may be filled back, partially or totally, with one or several materials.
FIGS. 1A to 1E are cross-section views illustrating different steps of a known method for manufacturing a MOS transistor on/in a very thin single-crystal silicon layer insulated from an underlying semiconductor layer.
FIG. 1A shows a semiconductor single-crystal silicon wafer 1 in which active regions 3 are defined by insulation areas 5. Areas 5 generally are trenches dug into wafer 1, then filled with an insulating material.
After this, a sacrificial single-crystal semiconductor layer 7 is grown. Layer 7 for example is a silicon-germanium layer (SiGe) containing from 20 to 40% of germanium. Close to the insulating periphery formed by insulation areas 5, the silicon-germanium grows with an angle which tends to draw it away from periphery 5. This results in a faceting 9 of the periphery. At the level of faceting 9, sacrificial layer 7 exhibits an irregular thickness. Only the central horizontal portion 11 of sacrificial layer 7 is homogeneous in terms of thickness.
Then, as illustrated in FIG. 1B, a semiconductor single-crystal silicon layer 13 is formed on sacrificial layer 7. Layer 13 generally exhibits a double faceting. FIG. 1B and the following ones illustrate such a double faceting, it being understood that silicon layer 13 may exhibit a single faceting or a more complex faceting. A faceting 15 is linked to the growth of layer 13 close to insulating periphery 5 and to the presence of underlying faceting 9. Another faceting 17 is present at the periphery of a central platform 19 of layer 13 which grows on central portion 11 of layer 7.
Then, as illustrated in FIG. 1C, gate 21 of a transistor is formed on layer 13. Gate 21 is insulated from underlying layer 13 by a thin insulator 22 and is surrounded with an insulating peripheral lateral spacer 23. Source/drain implantations are performed.
FIG. 2 is a top view corresponding to FIG. 1C. It shows facetted regions 15 and 17 around central portion 19 of layer 13 and insulated gate 21 which crosses active region 3 and bears on insulation areas 5. It should be noted that FIGS. 1A to 1E are cross-section views along axis I-I′ perpendicular to the extension axis of gate 21. As illustrated in FIG. 2, gate 21 passes twice on facetings 15 and 17 shown in dotted lines.
At this stage of the method, it is desired to remove sacrificial silicon-germanium layer 7. However, as illustrated in the cross-section view of FIG. 1C, SiGe layer 7 is still coated with Si layer 13. To be able to access to SiGe layer 7, Si layer 13 must thus be locally removed.
For this purpose, as illustrated in FIG. 1D, a specific mask M exhibiting a dimension greater than that of gate 21 but lower than that of layer 13 must be formed. Mask M is generally designed to only partially cover central portion 19 of layer 13 on either side of gate 21. The peripheral portion, illustrated in dotted lines, of silicon layer 13 is removed so that underlying sacrificial layer 7 is partially exposed.
Then, before or after removal of mask M, an etching capable of selectively eliminating silicon-germanium layer 7 is performed. After removal of layer 7, layer 13 is maintained in place by upper gate 21 which bears on insulation areas 5. The empty interval created by the removal of layer 7 is then kept to obtain a silicon substrate on nothing or filled with any appropriate element.
For example, as illustrated in FIG. 1E, an insulating material 25 which fills the interval between Si layer 13 and Si substrate 3 is deposited.
A MOS transistor comprising an insulated gate 21 and having a channel region 13 of low thickness, generally ranging between 5 and 20 nm, preferably lower than 10 nm, and typically on the order of 6 to 7 nm, is then obtained on a local insulator 25 of low thickness ranging between 10 and 30 nm, preferably approximately 10 nm.
Such a method exhibits various disadvantages which will be detailed in relation with FIG. 3, which illustrates the structure of FIG. 1E in cross-section view along plane III-III′ of FIG. 2 parallel to the extension axis of gate 21, perpendicular to cross-section axis I-I′ of FIGS. 1A to 1E. Thus, the portion of silicon layer 13 illustrated in FIG. 3 corresponds to a cross-section of the channel region under gate 21.
It can be seen in FIG. 3 that the channel of the MOS transistor formed by layer 13 exhibits significant thinnings on either side of its central portion 19 due to the existence of the above-mentioned facetings 9, 15, and 17. Further, such thinnings occur at a location where insulator 25 separating channel 13 from underlying active region 3 also exhibits a thinning. Such thinnings of channel 13 and of insulator 25 especially cause two types of malfunctions.
On the one hand, to the thinned channel areas corresponds a parasitic. MOS transistor having a threshold voltage much lower than that of the main central transistor formed at the level of horizontal portion 19 of layer 13. The unwanted premature turning-on of the peripheral parasitic transistor with respect to the central transistor is particularly disadvantageous.
On the other hand, the thinning of insulator 25 causes, close to periphery 5, that is, at the location where the structure is most fragile, a significant collapse of the equipotential lines in insulator 25. Insulator 25 is likely to breakdown and to short-circuit channel 13 and underlying active region 3.
Another disadvantage of the forming of the facetings lies in the pyramidal decrease in the horizontal central surface area of the upper layer. Thus, there appears from FIGS. 1A to 1E and 3 that central horizontal portion 11 of layer 7 is decreased with respect to the surface area of active region 3. Similarly, as illustrated in FIGS. 1B to 1E, 2 and 3, central portion 19 of layer 13 is smaller still. In cross-section view, with respect to active region 3; central portion 19 looses on each side from two to three times the sum of the thicknesses of layers 7 and 13. Thus, if the stacking of layers 7 and 13 exhibits a total thickness on the order of 30 nanometers, from 60 to 90 nm are lost on each side, that is, a total thickness from 120 to 180 nm. On design of the circuits, account needs to be taken of this decrease in the useful surface area with respect to the surface area of active region 3. This is an obstacle to the decrease in the device dimensions.
Further, the lost surface area increases along with the increase in the number of superposed layers. This is particularly disturbing on forming of multiple-layer structures such as, for example, multiple-gate transistors. This lost surface area also increases due to the fact that a non-self-aligned masking step needs to be provided.
The same problems as those described previously on forming of transistors exhibiting a gate of all-around type, in which the gate is formed all around a channel area, are encountered. In this case, the empty interval resulting from the removal of layer 7 is filled with an insulator and a gate conductor which surround channel 13.